Question 1-bit branch predictor Consider the following code Algorithm: // for (x1=3; x1 != 0; x1=x1-1) // x2 = x2 + x3 RISC-V code: 0000 addi x1, x0, 3 // x1 = 3 L: 0004 add x2, x2, x3 // x2 = x2 + x3 0008 subi x1, x1, 1 // x1 = x1 - 1 000C bne x1,0,L // if (x1 != 0) branch to L   Complete the following table showing the branch predictor behaviour (ONLY ANSWER ANYTHING DENOTED AS CHOOSE AND CHOOSE ONE OPTION). Note that * indicates an instruction fetch (IF) from a predicted branch. For simplicity, assume that a mis-predicted branch only costs one cycle (the fetch of the instruction following the branch mis-prediction). 1-Bit Branch Predictor Clock Cycle IF Address x1 Branch Predictor Value (start of cycle) Correct Prediction Branch Taken 0 0000         1 0004 3       2 0008         3 000C 2 0     4 000E*   0 no yes 5 0004   1     6 0008         7 000C 1 1     8 0004*   CHOOSE: 1 or 0 CHOOSE: yes or no CHOOSE: yes or no 9 0008         10 000C 0 CHOOSE: 1 or 0     11 0004*   CHOOSE: 1 or 0 CHOOSE: yes or no CHOOSE: yes or no 12 0010   CHOOSE: 1 or 0    

QNCF6A The Asker · Computer Science

1-bit branch predictor

Consider the following code

Algorithm:

// for (x1=3; x1 != 0; x1=x1-1)
// x2 = x2 + x3

RISC-V code:

0000 addi x1, x0, 3 // x1 = 3
L:
0004 add x2, x2, x3 // x2 = x2 + x3
0008 subi x1, x1, 1 // x1 = x1 - 1
000C bne x1,0,L // if (x1 != 0) branch to L

 

Complete the following table showing the branch predictor behaviour (ONLY ANSWER ANYTHING DENOTED AS CHOOSE AND CHOOSE ONE OPTION). Note that * indicates an instruction fetch (IF) from a predicted branch. For simplicity, assume that a mis-predicted branch only costs one cycle (the fetch of the instruction following the branch mis-prediction).

1-Bit Branch Predictor
Clock
Cycle
IF
Address
x1 Branch Predictor Value
(start of cycle)
Correct
Prediction
Branch
Taken
0 0000        
1

0004

3      
2

0008

       
3

000C

2 0    
4 000E*   0 no yes
5 0004   1    
6 0008        
7 000C 1 1    
8 0004*   CHOOSE: 1 or 0 CHOOSE: yes or no CHOOSE: yes or no
9 0008        
10 000C 0 CHOOSE: 1 or 0    
11 0004*   CHOOSE: 1 or 0 CHOOSE: yes or no CHOOSE: yes or no
12 0010   CHOOSE: 1 or 0    
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Community Answer
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【General guidance】The answer provided below has been developed in a clear step by step manner.Step1/3.jOOFPV{margin:0;font-family:"Aspira Webfont","Helvetica","Arial",sans-serif;display:-webkit-box;display:-webkit-flex;display:-ms-flexbox;display:flex;-webkit-flex-direction:column;-ms-flex-direction:column;flex-direction:column;gap:16px;}/*!sc*/data-styled.g746[id="sc-z3f5s1-0"]{content:"jOOFPV,"}/*!sc*/.drpmfd{white-space:pre-wrap;}/*!sc*/data-styled.g748[id="sc-1aslxm9-0"]{content:"drpmfd,"}/*!sc*/.kYdnkC{list-style:decimal;padding:0;margin-left:1.5em;}/*!sc*/data-styled.g767[id="sc-1aslxm9-19"]{content:"kYdnkC,"}/*!sc*/.hSgzqy{margin:0;font-family:"Aspira Webfont","Helvetica","Arial",sans-serif;}/*!sc*/data-styled.g777[id="sc-9wsboo-0"]{content:"hSgzqy,"}/*!sc*/.fjTYVF{margin:0;font-size:1rem;}/*!sc*/data-styled.g779[id="sc-1swtczx-0"]{content:"fjTYVF,"}/*!sc*/.dhvtXR{margin:0;font-family:"Aspira Webfont","Helvetica","Arial",sans-serif;line-height:normal;}/*!sc*/data-styled.g814[id="sc-1sugbjn-0"]{content:"dhvtXR,"}/*!sc*/At the beginning of cycle 1, the processor fetches the instruction at memory address 0x0000, which is an "addi" instruction that sets register x1 to 3. There is no branch prediction in this cycle, so the "Branch Predictor Value" column remains empty.At the beginning of cycle 2, the processor fetches the instruction at memory address 0x0004, which is an "add" instruction that adds the value of register x3 to the value of register x2. There is no branch instruction in this cycle, so the "Branch Predictor Value" column remains empty.At the beginning of cycle 3, the processor fetches the instruction at memory address 0x0008, which is a "subi" instruction that subtracts 1 from the value of register x1. There is no branch instruction in this cycle, so the "Branch Predictor Value" column remains empty.Explanation:Please refer to solution in this step.Step2/3.jOOFPV{margin:0;font-family:"Aspira Webfont","Helvetica","Arial",sans-serif;display:-webkit-box;display:-webkit-flex;display:-ms-flexbox;display:flex;-webkit-flex-direction:column;-ms-flex-direction:column;flex-direction:column;gap:16px;}/*!sc*/data-styled.g746[id="sc-z3f5s1-0"]{content:"jOOFPV,"}/*!sc*/.drpmfd{white-space:pre-wrap;}/*!sc*/data-styled.g748[id="sc-1aslxm9-0"]{content:"drpmfd,"}/*!sc*/.kYdnkC{list-style:decimal;padding:0;margin-left:1.5em;}/*!sc*/data-styled.g767[id="sc-1aslxm9-19"]{content:"kYdnkC,"}/*!sc*/.hSgzqy{margin:0;font-family:"Aspira Webfont","Helvetica","Arial",sans-serif;}/*!sc*/data-styled.g777[id="sc-9wsboo-0"]{content:"hSgzqy,"}/*!sc*/.fjTYVF{margin:0;font-size:1rem;}/*!sc*/data-styled.g779[id="sc-1swtczx-0"]{content:"fjTYVF,"}/*!sc*/.dhvtXR{margin:0;font-family:"Aspira Webfont","Helvetica","Arial",sans-serif;line-height:normal;}/*!sc*/data-styled.g814[id="sc-1sugbjn-0"]{content:"dhvtXR,"}/*!sc*/At the beginning of cycle 4, the processor fetches the instruction at memory address 0x000C, which is a "bne" instruction that checks whether the value of register x1 is equal to 0. If th ... See the full answer