QUESTION

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A CPU with a 24-bit address bus and 16-bit data bus implements the following memory blocks:
  $1 \mathrm{M}$   byte of   $\mathrm{ROM}$   using   $256 \mathrm{~K} \times 8$  -bit chips   $8 \mathrm{M}$   bytes of DRAM using   $2 \mathrm{M} \times 4$  -bit chips Design an address decoder to implement this arrangement.


A CPU with a 24-bit address bus and 16-bit data bus implements the following memory blocks: 1 M byte of ROM using $256 \mathrm{~K} \times 8$-bit chips $8 \mathrm{M}$ bytes of DRAM using $2 \mathrm{M} \times 4$-bit chips Design an address decoder to implement this arrangement.

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