Question Exercise 6. [20 Marks] Consider again the single-cycle MIPS datapath with control signals as presented in Figure 1. We want to add a new instruction to the MIPS instruction set architecture: foo. Its specification is as follows: MIPS assembly RTL foo $rd, $rs, $rt Reg[$rt] <- Mem[Reg[$rd]] Mem[Reg[$rd]] <- Reg[$rs] + Reg[$rt] PC <- PC + 4* Your task is to modify the MIPS datapath so that it can fulfill this new instruction foo. To do that, you should: (i) add new wires, ports, circuitry, MUX, control signals, etc. to the datapath so that it can execute the new instruction foo (see, e.g., Slides 16-23 in L11-CPUControl); (ii) ensure that any newly added circuitry and control signals do not hinder the execution of any existing operations in the MIPS ISA (i.e. your modified datapath should still be able to successfully execute all the preexisting instructions in the MIPS ISA). Assume that memory is fast enough to read and write within one clock cycle, and that the read from memory occurs before the write to memory. To structure your solution to this exercise, perform the following: (c) Give the values of the control signals required to execute your instruction. That is, when executing the foo instruction, give the values of the 8 preexisting control signals as well as the values of any new control signals you have added.
Exercise 6. [20 Marks] Consider again the single-cycle MIPS datapath with control signals as presented in Figure 1. We want to add a new instruction to the MIPS instruction set architecture: foo. Its specification is as follows:
| MIPS assembly | RTL |
| foo $rd, $rs, $rt |
Reg[$rt] <- Mem[Reg[$rd]] Mem[Reg[$rd]] <- Reg[$rs] + Reg[$rt] PC <- PC + 4* |
Your task is to modify the MIPS datapath so that it can fulfill this new instruction foo. To do that, you should: (i) add new wires, ports, circuitry, MUX, control signals, etc. to the datapath so that it can execute the new instruction foo (see, e.g., Slides 16-23 in L11-CPUControl); (ii) ensure that any newly added circuitry and control signals do not hinder the execution of any existing operations in the MIPS ISA (i.e. your modified datapath should still be able to successfully execute all the preexisting instructions in the MIPS ISA). Assume that memory is fast enough to read and write within one clock cycle, and that the read from memory occurs before the write to memory. To structure your solution to this exercise, perform the following:
(c) Give the values of the control signals required to execute your instruction. That is, when executing the foo instruction, give the values of the 8 preexisting control signals as well as the values of any new control signals you have added.
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