Question Exercise 6. [20 Marks] Consider again the single-cycle MIPS datapath with control signals as presented in Figure 1. We want to add a new instruction to the MIPS instruction set architecture: foo. Its specification is as follows: MIPS assembly RTL foo $rd, $rs, $rt Reg[$rt] <- Mem[Reg[$rd]] Mem[Reg[$rd]] <- Reg[$rs] + Reg[$rt] PC <- PC + 4* Your task is to modify the MIPS datapath so that it can fulfill this new instruction foo. To do that, you should: (i) add new wires, ports, circuitry, MUX, control signals, etc. to the datapath so that it can execute the new instruction foo (see, e.g., Slides 16-23 in L11-CPUControl); (ii) ensure that any newly added circuitry and control signals do not hinder the execution of any existing operations in the MIPS ISA (i.e. your modified datapath should still be able to successfully execute all the preexisting instructions in the MIPS ISA). Assume that memory is fast enough to read and write within one clock cycle, and that the read from memory occurs before the write to memory. To structure your solution to this exercise, perform the following: (d) If you have added any new control signals, give the values of these control signals when any instruction besides foo is being executed.

F5VOAH The Asker · Computer Science

Exercise 6. [20 Marks] Consider again the single-cycle MIPS datapath with control signals as presented in Figure 1. We want to add a new instruction to the MIPS instruction set architecture: foo. Its specification is as follows:

MIPS assembly

RTL

foo $rd, $rs, $rt

Reg[$rt] <- Mem[Reg[$rd]]

Mem[Reg[$rd]] <- Reg[$rs] + Reg[$rt]

PC <- PC + 4*

Your task is to modify the MIPS datapath so that it can fulfill this new instruction foo. To do that, you should: (i) add new wires, ports, circuitry, MUX, control signals, etc. to the datapath so that it can execute the new instruction foo (see, e.g., Slides 16-23 in L11-CPUControl); (ii) ensure that any newly added circuitry and control signals do not hinder the execution of any existing operations in the MIPS ISA (i.e. your modified datapath should still be able to successfully execute all the preexisting instructions in the MIPS ISA). Assume that memory is fast enough to read and write within one clock cycle, and that the read from memory occurs before the write to memory. To structure your solution to this exercise, perform the following:

(d) If you have added any new control signals, give the values of these control signals when any instruction besides foo is being executed.

More

Community Answer

YN1M89

Null Hypthesis Sayd that there is no Statistical Significanee bjw the two variable in the hytothesis when eriticle value less then the rest Statistic value, then we conclude that given data is Sufficient for reject the claim.The alterna ... See the full answer