# Question Given the following Verilog description. Draw the logic diagram of the given Verilog HDL description including the content of the submodule. Label all the inputs and outputs of each gate clearly in the diagram. module Problem5(x,y,a,b,c); input a, b, c; output x, y; wire t1, t2, t3; sub ({a, b, c}, {t1, t2}); assign t3 = t1 & t2; sub ({t3, t1, t2}, {x, y}); endmodule module sub(A, F); input [2:0] A; output [1:0] F; wire a, b, c; assign {a, b, c} = A; nor 01(F[0], a, b); | or o2(F[1], a, *c); endmodule

PA5C4S The Asker · Electrical Engineering

Transcribed Image Text: Given the following Verilog description. Draw the logic diagram of the given Verilog HDL description including the content of the submodule. Label all the inputs and outputs of each gate clearly in the diagram. module Problem5(x,y,a,b,c); input a, b, c; output x, y; wire t1, t2, t3; sub ({a, b, c}, {t1, t2}); assign t3 = t1 & t2; sub ({t3, t1, t2}, {x, y}); endmodule module sub(A, F); input [2:0] A; output [1:0] F; wire a, b, c; assign {a, b, c} = A; nor 01(F[0], a, b); | or o2(F[1], a, *c); endmodule
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Transcribed Image Text: Given the following Verilog description. Draw the logic diagram of the given Verilog HDL description including the content of the submodule. Label all the inputs and outputs of each gate clearly in the diagram. module Problem5(x,y,a,b,c); input a, b, c; output x, y; wire t1, t2, t3; sub ({a, b, c}, {t1, t2}); assign t3 = t1 & t2; sub ({t3, t1, t2}, {x, y}); endmodule module sub(A, F); input [2:0] A; output [1:0] F; wire a, b, c; assign {a, b, c} = A; nor 01(F[0], a, b); | or o2(F[1], a, *c); endmodule