Question Problem 5: Given the following Verilog description. Draw the logic diagram of the given Verilog HDL description including the content of the submodule. Label all the inputs and outputs of each gate clearly in the diagram. module Problem5(x,y,a,b,c); input a, b, c; output x, y; wire t1, t2, t3; sub ({a,b,c}, {t1, t2}); assign t3 = t1 & t2; sub ({t3, t1, t2}, {x,y}); endmodule module sub( A, F); input (2:0) A; output (1:0) F; wire a, b, c; assign {a,b,c} = A; nor 01(F[0], a, b); or 02(F[1], a, c); endmodule

First of all I would like to explain the \operatorname{code}Code:Explanation:Module name: sub and its input & outputs wereA, F \text {. }Declaring A as input also vector of length 3 .Decbring F as output and also as vector of length 2 .Decbring a, b, c as wires; one-bit wires.\operatorname{assign}\{a, b, c\}=AAssigning values of a, b, c as following:\begin{array}{l}a=A[2] \\b=A[1] \\c=A[0]\end{array}View image!Then circuit diagram will be as follows:Then code explanation for problem 5 modue:Codemodule problems (x, y, a, b, c)\frac{\pi}{i n p h t r a, b, c}ExplanationModule Name: Problem 5 and input, outputs care. x, y, a, b, c.Declaring a, b, c as inputs.Declaieng x, y as outputs.wive t_{1}, t_{2}, t_{3} ;Declaring t 1, t_{2}, t 3 as one bit wires.View image!CodeGplanation\operatorname{sub}\left(\{a, b, c\},\left\{t_{1}, t_{2}\right\}\right) (But this won'l work)Because we have to give some rame to the submodule)Correct code isub x I(\{a, b, c\},\{t, 1, t))sub x I(\{a, b, c\},\{t, t\}\},\operatorname{assign} \quad t_{3}=t_{1} \& t_{2}\operatorname{sub}\left(\left\{t_{3}, t_{1}, t_{2}\right\},\{x, y\}\right)(Bod this wont work because of two sub-rodules with samenoine so, we have to give some name)Correct code:Sub \times 2\left(\left\{t_{3} t_{11} t_{2}\right\}\left\{\left\{21 y_{1}\right)\right.\right.Declasing a, b, c as inputs to previous submodule\begin{array}{l}\Rightarrow \quad a=A[a] \\\}_{\text {sub madule }} \\\end{array}Declaing t_{1}, t_{2} as output to previous submodule\begin{array}{l} \Rightarrow F[0]=t_{2} \quad \\\left.F[1]=t_{1} \quad\right\} \rightarrow x_{1} \\\text { sub nodule }\end{array}Assinging\begin{array}{l}t_{3}=t_{1} \cdot t_{2} \\t_{3}=F(\Phi) \cdot F(0)\end{array}Declaaing t_{3}, t_{1}, t_{2} as inputs to previous submodule as follows:\begin{array}{l} \Rightarrow t_{3}=A[2] \\t_{1}=A[1] \\b_{2}=A[0] \quad \rightarrow x_{2} \\\text { sub module. }\end{array}Deklaring x, y as autputs of previous sabiodua:\begin{array}{l}\Rightarrow F[i]=x \quad\}_{s u} \\F[0]=y \quad{ }^{5} \text { sub module } \\\end{array}End modileModule was ended.View image!Then the cirait diagrams will be as follows:View image!If you clicked on that phes symbd, then circuit will be as follows:From circuit diagram:\begin{aligned}t_{2} & =\overline{(a+b)}, t_{1}=a+\bar{c}, t_{3}=t_{2} \cdot t_{1} \\t_{3} & =\overline{(a+b)} \cdot(a+\bar{c}) \\& =\left(a^{\prime} \cdot b^{\prime}\right)(a+\bar{c}) \quad\left(\because \overline{(M+N)}=M^{\prime} N^{\prime}\right) \\t_{3} & =a^{\prime} a b^{\prime}+a^{\prime} b^{\prime} c^{\prime}=a^{\prime} b^{\prime} c^{\prime} \quad\left(\because M \cdot M^{\prime}=0\right)\end{aligned}View image!\begin{aligned} \therefore y & =\overline{\left(t_{3}+t_{1}\right)} \\ & =\overline{\left(a^{\prime} b^{\prime} c^{\prime}+a+c^{\prime}\right)} \\ & =\overline{\left(c^{\prime}\left(1+a^{\prime} b^{\prime}\right)+a\right)} \\ & =\overline{\left(c^{\prime}+a\right)} \quad\left(\because 1+M^{\prime} N^{\prime}=I\right) \\ & =\left(c^{\prime}\right)^{\prime} \cdot a^{\prime} \quad\left(\because \overline{(M+N)}=M^{\prime} \cdot N\right) \\ y & =c \cdot a^{\prime}\end{aligned}\begin{aligned} \therefore x & =t_{3}+\overline{t_{2}} \\ & =a^{\prime} b^{\prime} c^{\prime}+\overline{(a+b)} \\ & =a^{\prime} b^{\prime} c^{\prime}+a^{\prime} \cdot b^{\prime} \quad\left(\because \overline{(M+N)}=M^{\prime} N N^{\prime}\right) \\ & =a^{\prime} b^{\prime}\left(1+c^{\prime}\right) \\ x & =a^{\prime} b^{\prime} \quad\left(\because 1+M^{\prime}=1\right)\end{aligned}View image! ...