Problems 3.2(e,f), 3.4(e,f), 3.5(b,c), 3.6(c,d), 3.10(a,b),
3.11, 3.12(b), 3.15(a,c)
140 Chapter 3 Gate-Level Minimization Problems 141 3.4 Simplify the following Boolean functions, using K-maps: (a) F(x,y, z) (2,3.6,7) (c)' F(A,B,C,D)=Σ(3,7, ll, 13, 14, 15) (e) F (w, x, y, z) = Σ(11, 12, 13, 14, 15) (g) F(w, x, y, z)=E(0.1.4,5,10,1 1,14,15) Simplify the following Boolean functions, using four-variable K-maps: (a)" F (w, x, y, z) = Σ(1, 4, 5, 6, 12, 14, 15) (b)" F (A, B, C, D) = Σ(2, 3, 6, 7, 12, 13, 14) (c) F (w, x, y, z) = Σ(1, 3, 4, 5, 6, 7, 9, 1 1, 13, 15) (d)' F (A, B, C, D) = Σ (0, 2, 4, 5, 6, 7, 8, 10, 13, i5) Simplify the following Boolean expressions, using four-variable K-maps: (a) A'B'C'D AC'D' B'CDA'BCD BCD (by (d)' (f) (h) F (A, B, C, D) = Σ(4. 6, 7, 15) F(w.rry, z)_E(2.3. I2. 13, 14, 15) F (w, x, y, z)-S(8, 10, 12, 13.4) F(w, x, y, z)-E(2.3.6.7.8.9.12,I3) UDP 02467 3.5 FIGURE 3.40 Schematic for Circuit with UDP_02467 3.6 Although Verilog HDL uses this kind of description for UDPs only, other HDLs and computer-aided design (CAD) systems use other procedures to specify digital circuits in tabular form. The tables can be processed by CAD software to derive an efficient gate structurc of the design. None of Verilog's predefined primitives describes sequential logic. The model of a sequential UDP requires that its output be declared as a reg data type, and that a column be added to the truth table to describe the next state. So the columns are organized as inputs: state: next state. (c) A'B'CD AB'D +A'BC ABCD AB'C (d) A'B'C'D' BC'D A'C'D A'BCD +ACD' Simplify the following Boolean expressions, using four-variable K-maps: 3.7 In this section, we introduced the HDLs and presented simple examples to illustrate alternatives for modeling combinational logic. A more detailed presentation of model- ing with HDLs can be found in the next chapter. The reader familiar with combinational circuits can go directly to Section 4.12 to continue with this subject. (c) AB C B'C'DBCD ACD'+ A'B'C+ A BC D Find the minterms of the following Boolean expressions by first plotting each function in a K-map: 3.8 (a) xy yz + xy'z (b) C'D+ABC ABD' +A'B'D (d) A'B A'CD B'CD BC'D VHDL-Truth Tables 3.9 Find all the prime implicants for the following Boolean functions, and determine which are essential: (a)" F(w, x, y, z) = Σ(0, 2, 4, 5, 6, 7, 8, 10, 13, 15) (b), F (A, B, C, D) = Σ(0, 2, 3, 5, 7, 8, 10, 11, 14, 15) (c) F (A, B, C, D) = Σ(2, 3, 4, 5, 6, 7, 9, 11, 12, 13) (d) F(w,x, y, z)=E(1.3, 6, 7, 8, 9, 12, 13, 14, 15) (e) F (A, B, C, D) = Σ(0, 1, 2, 5, 7, 8, 9, 10, 13, 15) (f) F(w, x, y, z)=E(0.1, 2, 5, 7, 8, 10, 15) Simplify the following Boolean functions by first finding the essential prime implicants: (a) F (w, x, y, z) 2(0, 2, 5, 7, 8, 10, 12, 13, 14, 15) (b) F(A, B,C, D) 2(0,2,3,5,7,8,10, 11, 14, 15) (e)* F(A, B,C,D)-(1,3,4,5, 10, 11, 12, 13, 14, 15) (d) F (w, x, y, z) = Σ(0, 1, 4, 5, 6, 7, 9, 11, 14, 15) (e) F (A, B, C, D)-Σ(0.1, 3, 7, 8, 9, 10, 13, 15) (f) F (w, x, y, z) = Σ(0, 1, 2, 4, 5, 6, 7, 10, 15) VHDL does not support truth tables directly. Instead, a truth table has to be converted into a set of Boolean equations, which can be described by signal assignment statements. PROBLEMS (Answers to problems marked with appear at the end of the text.) 3.10 1 Simplify the following Boolean functions, using three-variable K-maps: (a) F(x, y, z) = Σ (0, 2, 4, 5) (c) Fr, y, )-20,1,2,3, 5) (b) F(x,y, z)-2(0, 2, 4, 5, 6) (d) , y, z)=E(1,2,3,7) 2 Simplify the following Boolean functions, using three-variable K-maps: (b)" F(x, y, z) = Σ(1, 2, 3, 6, 7) (d) F(x, y, z) = Σ( 1, 2, 3, 5, 6, 7) (f) F(x, y, z)=E(3, 4, 5, 6, 7) (a)" F(x, y, z) = Σ (0, 1, 5, 7) (c) Fx,y, z) (2,3,4,5) (e) P(x, y, z) = Σ(0,2,4,6) Simplify the following Boolean expressions, using three-variable K-maps: (a)'. F (x.yz) = xy + x'y'z, + χ,yz (c)" F (x, y, z) = x,y + yz' + y,z' 3.11 Using K-maps for Fand F,convert the following Boolean function from a sum-of-prod- 3.3 ucts form to a simplified product-of-sums form. (d) F(x, y, z) = x,yz + xy,z' + xy'z F(w ryz)0,,2, 5,8, 10, 13)