**QUESTION**

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1. An inverter (NOT) gate is designed with $\mathrm{tHL}_{\mathrm{HL}}=0.25 \mathrm{~ns}$ and $\mathrm{tLH}_{\mathrm{L}}=0.5 \mathrm{~ns}$. The input voltage $\mathrm{V}_{\text {in }}$ is shown in accompanying figure, and is known that the output voltage ranges from $\mathrm{V}_{\text {out }}=0 \mathrm{v}$ to $\mathrm{V}_{\text {out }}=5 \mathrm{v}$. (15pts) (a) Draw a waveform for $\mathrm{V}_{\text {out }}(\mathrm{t})$. (b) What is the maximum switching frequency for this circuit, if $90 \%$ and $10 \%$ of $\mathrm{VDD}_{\mathrm{DD}}$ are used as threshold voltage levels for logic 1 and 0 , respectively? Draw a waveform of the output voltage $\mathrm{V}_{\text {out }}$ at this frequency. (c) Suppose that the input is driven at twice the maximum frequency. Draw a waveform of the output voltage in this case, and explain why the gate will not operate properly.