*10.60 Consider the CMOS inverter circuit shown in Figure 10.59a. Ideal n- and p-channel devices are to be designed with channel lengths of $L=2.5 \mu \mathrm{m}$ and oxide thicknesses of $t_{\mathrm{ox}}=450 \AA$. Assume the inversion channel mobilities are one-half the bulk values. The threshold voltages of the $\mathrm{n}$ - and $\mathrm{p}$-channel transistors are to be $+0.5 \mathrm{~V}$ and $-0.5 \mathrm{~V}$, respectively. The drain current is to be $I_{D}=0.256 \mathrm{~mA}$ when the input voltage to the inverter is $1.5 \mathrm{~V}$ and $3.5 \mathrm{~V}$ with $V_{D D}=5 \mathrm{~V}$. The gate material is to be the same in each device. Determine the type of gate, substrate doping concentrations. and channel widths.

1. For two $n \times n$ matrices $\mathbf{A}$ and $\mathbf{B}$, prove that (a) $(\mathbf{A B})^{\top}=\mathbf{B}^{\top} \mathbf{A}^{\top}$; (b) $(\mathbf{A B})^{\dagger}=\mathbf{B}^{\dagger} \mathbf{A}^{\dagger}$; and (c) $(\mathrm{AB})^{-1}=\mathrm{B}^{-1} \mathrm{~A}^{-1}$,

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