(a) Calculate the delay in terms of full-adder block delays, in producing product bit p7 in each of the 4 x 4 multiplier arrays in Figure 9.16. Ignore the AND gate delay to generate all miqj products at beginning.
(b) Develop delay expressions for each of the arrays in Figure 9.16 in terms of n for the n x n case as an extension of part (a) of the problem. Then use these expressions to calculate delay for the 32 x 32 case for each array.
354 (a) Ripple-carry array (b) Carry-save array Figure 9.16 Ripple-carry and carry-save arrays for a $4 \times 4$ multiplier.
(a) Ripple-carry array