Step 1

Enable the interrupt number 31.

LDR r11, [r8, #IOData] ;Load port data from the IO

; device.

STR r11, [r9], #4 ; Store it to memory: update

; the pointer.

CMP r9, r10 ; Reached the end ?

SUBLSS pc, lr, #4 ; No, so return.

; Insert transfer complete

; code here.

LDR r13, [r8, #IOStat] ; Load status register to find which port ; caused the interrupt.

TST r13, #IOPort1Active LDREQ r13, [r8, #IOPort1] ; Load port 1 data.

LDRNE r13, [r8, #IOPort2] ; Load port 2 data.

STREQ r13, [r9], #4 ; Store to buffer 1.

STRNE r13, [r10], #4 ; Store to buffer 2.

CMP r9, r11 ; Reached the end?

CMPLE r10, r12 ; On either channel?

SUBNES pc, lr, #4 ; Return ;

Insert transfer complete code here.

; first save the critical state SUB lr, lr, #4 ; Adjust the return address ; before we save it.

STMFD sp!, {lr} ; Stack return address

MRS r14, SPSR ; get the SPSR ...

STMFD sp!, {r12, r14} ; ... and stack that plus a ; working register too. ; Now get the priority level of the ; highest priority active interrupt.

MOV r12, #IntBase ; Get the interrupt controller's ; base address.

LDR r12, [r12, #IntLevel] ; Get the interrupt level (0 to 31). ; Now read-modify-write the CPSR to enable interrupts.

MRS r14, CPSR ; Read the status register.

BIC r14, r14, #0x80 ; Clear the I bit ; (use 0x40 for the F bit).

MSR CPSR_c, r14 ; Write it back to re-enable ; interrupts and

LDR PC, [PC, r12, LSL #2] ; jump to the correct handler. ; PC base address points to this ; instruction + 8

NOP ; pad so the PC indexes this table. ; Table of handler start addresses

DCD Priority0Handler

DCD Priority1Handler

DCD Priority2Handler ; ... Priority0Handler

STMFD sp!, {r0 - r11} ; Save other working registers. ; Insert handler code here. ; ...

LDMFD sp!, {r0 - r11} ; Restore working registers (not r12). ; Now read-modify-write the

CPSR to disable interrupts. MRS r12,

CPSR ; Read the status register.

ORR r12, r12, #0x80 ; Set the I bit ; (use 0x40 for the F bit).

MSR CPSR_c, r12 ; Write it back to disable interrupts. ; Now that interrupt disabled, can safely restore

SPSR then return.

LDMFD sp!, {r12, r14} ; Restore r12 and get SPSR.

MSR SPSR_csxf, r14 ; Restore status register from r14.

LDMFD sp!, {pc}^ ; Return from handler. Priority1Handler ; ...

Step 2

Sets its priority bits to 2-

PUSH {R0-R2, LR}

AND R1, R0, #0x1F ; Generate enable bit pattern for

; the IRQ

MOV R2, #1

LSL R2, R2, R1 ; Bit pattern = (0x1 << (N & 0x1F))

AND R1, R0, #0xE0 ; Generate address offset if IRQ number

; is above 31

LSR R1, R1, #3 ; Address offset = (N/32)∗4 (Each word

; has 32 IRQ enable)

LDR R0,=0xE000E100 ; SETEN register for external interrupt

; #31-#0

STR R2, [R0, R1] ; Write bit pattern to SETEN register

POP {R0-R2, PC} ; Restore registers and Return

ENDFUNC

Similarly, we can create a function DisableIRQ to disable an interrupt:

; A subroutine to disable an IRQ based on IRQ number

DisableIRQ FUNCTION

; Input R0 = IRQ number

PUSH {R0-R2, LR}

AND R1, R0, #0x1F ; Generate enable bit pattern for

; the IRQ

MOV R2, #1

LSL R2, R2, R1 ; Bit pattern = (0x1 << (N & 0x1F))

AND R1, R0, #0xE0 ; Generate address offset if IRQ number

; is above 31

LSR R1, R1, #3 ; Address offset = (N/32)∗4 (Each word

; has 32 IRQ enable)

LDR R0,=0xE000E180 ; CLREN register for external interrupt

; #31-#0

STR R2, [R0, R1] ; Write bit pattern to SETEN register

POP {R0-R2, PC} ; Restore registers and Return

ENDFUNC

To configure the priority of an interrupt, we can take advantage of the fact that the interrupt priority registers are byte addressable, making the coding much easier. For example, to set IRQ #4 priority level to 0xC0, we can use the following code:

; Setting IRQ #4 priority to 0xC0

LDR R0, =0xE000E400 ; External Interrupt Priority Register

; starting address

MOVS R1, #0xC0 ; Priority level

STRB R1, [R0, #4] ; Set IRQ #4 priority

Step 3

Clears its pending bit disable the interrupt 31:-

PUSH {R1, R2}

LDR R1,=0xE000E200 ; NVIC SETPEND

MOVS R2, #1

LSLS R2, R2, R0

STR R2, [R1]

POP {R1, R2}

BX LR ; Return

ENDFUNC

;-------------------------

; Clear IRQ Pending

; - input R0 : IRQ number. E.g. IRQ#0 = 0

ALIGN

nvic_clr_pending FUNCTION

PUSH {R1, R2}

LDR R1,=0xE000E280 ; NVIC CLRPEND

MOVS R2, #1

LSLS R2, R2, R0

STR R2, [R1]

POP {R1, R2}

BX LR ; Return

ENDFUNC

;-------------------------

Write an assembly code that performs the following four tasks: enable the interrupt number 31, and sets its priority bits to 2, and clears its pending bit disable the interrupt 31 (Hints: Each interrupt has one enable bit, one pending bit, and one byte of priority.)

Public Answer

Write an assembly code that performs the following four tasks:

enable the interrupt number 31, and

sets its priority bits to 2, and

clears its pending bit

disable the interrupt 31

(Hints: Each interrupt has one enable bit, one pending bit, and one byte of priority.)